PAX-128

PAX-128 consists of a Host computer, Control unit, and PU(processings unit) array. PUs were connected in 8 x 16 two-dimensional torus grid. Inter PU communication between two neiboring PUs is performed through a 2KB shared memory. Host computer and Control unit are shared with PAX-32.
System configuration of PAX-128 and PAX-32 [44KB]
A processing unit has an 8-bit microprocessor (M68B00), a floating point unit (AM9511-4) and 32KBytes of memory. Each PU has a register for quick barrier synchronization. Peak performance of a PU is about 0.03Mflops.

Cross Compiler of SPL/M developped for PAX-32 is used also for PAX-128.

Peak performance of PAX-128 is 4 Mflops on solving Poissson equation.

PAX-128 was developed at the University of Tsukuba in 1983, with the fund of 6.4M yen (about 25K US$) by putting together two funds provided to Prof.T.Hoshino and to Prof.T.Kawai by Grant-in-Aid of the Ministry of Eduation, Science and Culture. PAX-128 was constructed by Prof. T.Hoshino and his family, Dr.T.Shirakawa, and four students.

Photo:

Test set of two PUs [13KB]
Constructing PAX-128 [10KB]
Inside of PAX-128 [16KB]
Front Panel of PAX-128 [40KB]
Side-front view of PAX-128 [37KB]
PU board of PAX-128 [370KB]

* flops : float(single precision) operations per second peak performance.