PAX-64J consists of a host computer and a PU(processings unit) array.
PAX-64J consists of a host computer and a PU(processings unit) array.
The host computer is a 16-bit mini-computer (left half in the photo).
PU array is at the right half in the photo, but it is hidden behind the cables for column-wise nearest neighbor connection.
PU array has 32 PU connected in 4 x 8 two-dimensional torus.
Each PU has a 16-bit microprocessor of same architecture
as the Host computer.
Each PU has 136KBytes of memory.
As the host computer and the microprocessor on a PU has same architecture, FORTRAN77 compiler for the host computer is also used to develop the codes for the PU.
Peak performance of PAX-64J was 3.2 Mflops on solving Poissson equation.
PAX-64J was made at the University of Tsukuba in 1984. It was constructed by Mitsui Engineering and Shipbuilding Co.,Ltd.