P.R. Panda, H. Nakamura, N.D. Dutt, and A. Nicolau : "Improving Cache Performance through Tiling and Data Alignment", Lecture Notes in Computer Science, pp167-185, Vol 1253, Springer-Verlag, Also appeared in IRREGULAR'97 Synposium, 1997
H.Nakamura, K.Itakura, M.Matsubara, T.Boku, and K.Nakazawa : "Effectiveness of Register Preloading on CP-PACS Node Processor", International Workshop on Innovative Architecture 97, pp. 83-90, Maui, USA , January 1997
P.R. Panda, H. Nakamura, N.D. Dutt, and A. Nicolau : "A Data Alignment Technique for Improving Cache Performance", Proc. of IEEE International Conference on Computer Design (ICCD '97), pp.587-592, , Austin, USA, October 1997
K.Kurata and H.Nakamura, : "Novel Method for Primer/Probe Design and Sequence Analysis", Genome Informatics 11, pp.331-332, , Tokyo, Japan, December, 2000
M. Kondo, H. Okawara, H.Nakamura, and T. Boku, : "SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing", Proc. of IEEE International Conference on Computer Design (ICCD 2000), pp.105-111, , Austin, USA, September 2000
H.Nakamura, M.Kondo, and T.Boku, : "Software Controlled Reconfigurable On-Chip Memory for High Performance Computing", Lecture Notes in Computer Science, pp.15-32, Vol. 2107, Springer-Verlag, Also appeared in 2nd Workshop on Intelligent Memory Systems (IMS 2000), Cambridge, USA, November, 2000
M. Fujita, and H. Nakamura : "The Standard SpecC Language", Proc. of ACM/IEEE International Symposium on System Synthesis 2001, pp. 81-86, Montreal, Canada, October, 2001
N. Hosaka, K. Kurata, and H. Nakamura, : "Comparison of Methods for Probe Design", Genome Informatics 12, pp.449-450,, Tokyo, Japan, December, 2001
M. Kondo, M. Fujita, H. Nakamura : "Software-Controlled On-Chip Memory for High-Performance and Low-Power Computing", ACM SIGARCH Computer Architecture News, Vol. 30, Issue 3, pp.7-8,, Also appeared in HPCA-8 Work-in-progress Session, Cambridge, USA, June, 2002
K.Kurata, V.Breton, and H.Nakamura : "A method to find unique sequences on Distributed Genome Database", Proc. of CCGrid 2003 (Cluster Computing and Grid), pp.62-69,, Tokyo, Japan, May 2003
M. Kondo, M. Iwamoto, and H. Nakamura : "Cache Line Impact on 3D PDE Solvers", Lecture Notes in Computer Science 2327, pp.301-309, , Also appeared in International Symposium on High Performance Computing (ISHPC 2002), Nara, Japan, May 2002
M. Kondo, S. Tanaka, M. Fujita, and H. Nakamura : "Reducing Memory System Energy in Data Intensive Computations by Software-Controlled On-Chip Memory", Workshop on Compilers and Operating Systems for Low Power in conjunction with PACT02, Charlottesville, USA, September 2002
T. Ohneda, M. Kondo, M. Imai, H. Nakamura, : "Design And Evaluation Of High Performance Microprocessor With Reconfigurable On-Chip Memory", IEEE Asia-Pacific Conference on Circuits and Systems 2002, pp.211-216,, Singapore, Dec. 2002
C. Takahashi, M. Kondo, T. Boku, D. Takahashi, H. Nakamura, and M. Sato : "SCIMA-SMP: on-chip memory processor architecture for SMP", Proc. 3rd Workshop on Memory Performance Issues (WMPI-2004), Munich, Germany, Jun. 2004