Papers published from Center for Computational Physics, University of Tsukuba
/Computer Science
/Papers on High Performance Processor Architecture
/
proceedings and reviews in English
Improving Cache Performance through Tiling and Data Alignment
- Authors: P.R. Panda, H. Nakamura, N.D. Dutt, and A. Nicolau
- Published: Lecture Notes in Computer Science, pp167-185, Vol 1253, Springer-Verlag
- Venue: Also appeared in IRREGULAR'97 Synposium
- Date: 1997
Effectiveness of Register Preloading on CP-PACS Node Processor
- Authors: H.Nakamura, K.Itakura, M.Matsubara, T.Boku, and K.Nakazawa
- Published: International Workshop on Innovative Architecture 97, pp. 83-90
- Venue: Maui, USA
- Date: January 1997
A Data Alignment Technique for Improving Cache Performance
- Authors: P.R. Panda, H. Nakamura, N.D. Dutt, and A. Nicolau
- Published: Proc. of IEEE International Conference on Computer Design (ICCD '97), pp.587-592,
- Venue: Austin, USA
- Date: October 1997
Novel Method for Primer/Probe Design and Sequence Analysis
- Authors: K.Kurata and H.Nakamura,
- Published: Genome Informatics 11, pp.331-332,
- Venue: Tokyo, Japan
- Date: December, 2000
SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing
- Authors: M. Kondo, H. Okawara, H.Nakamura, and T. Boku,
- Published: Proc. of IEEE International Conference on Computer Design (ICCD 2000), pp.105-111,
- Venue: Austin, USA
- Date: September 2000
Software Controlled Reconfigurable On-Chip Memory for High Performance Computing
- Authors: H.Nakamura, M.Kondo, and T.Boku,
- Published: Lecture Notes in Computer Science, pp.15-32, Vol. 2107, Springer-Verlag
- Venue: Also appeared in 2nd Workshop on Intelligent Memory Systems (IMS 2000), Cambridge, USA
- Date: November, 2000
The Standard SpecC Language
- Authors: M. Fujita, and H. Nakamura
- Published: Proc. of ACM/IEEE International Symposium on System Synthesis 2001, pp. 81-86
- Venue: Montreal, Canada
- Date: October, 2001
Comparison of Methods for Probe Design
- Authors: N. Hosaka, K. Kurata, and H. Nakamura,
- Published: Genome Informatics 12, pp.449-450,
- Venue: Tokyo, Japan
- Date: December, 2001
Software-Controlled On-Chip Memory for High-Performance and Low-Power Computing
- Authors: M. Kondo, M. Fujita, H. Nakamura
- Published: ACM SIGARCH Computer Architecture News, Vol. 30, Issue 3, pp.7-8,
- Venue: Also appeared in HPCA-8 Work-in-progress Session, Cambridge, USA
- Date: June, 2002
A method to find unique sequences on Distributed Genome Database
- Authors: K.Kurata, V.Breton, and H.Nakamura
- Published: Proc. of CCGrid 2003 (Cluster Computing and Grid), pp.62-69,
- Venue: Tokyo, Japan
- Date: May 2003
Cache Line Impact on 3D PDE Solvers
- Authors: M. Kondo, M. Iwamoto, and H. Nakamura
- Published: Lecture Notes in Computer Science 2327, pp.301-309,
- Venue: Also appeared in International Symposium on High Performance Computing (ISHPC 2002), Nara, Japan
- Date: May 2002
Reducing Memory System Energy in Data Intensive Computations by Software-Controlled On-Chip Memory
- Authors: M. Kondo, S. Tanaka, M. Fujita, and H. Nakamura
- Published: Workshop on Compilers and Operating Systems for Low Power in conjunction with PACT02
- Venue: Charlottesville, USA
- Date: September 2002
Design And Evaluation Of High Performance Microprocessor With Reconfigurable On-Chip Memory
- Authors: T. Ohneda, M. Kondo, M. Imai, H. Nakamura,
- Published: IEEE Asia-Pacific Conference on Circuits and Systems 2002, pp.211-216,
- Venue: Singapore
- Date: Dec. 2002